1. Field of the Invention
The present invention relates to the testing of complex integrated circuits and, in particular, to a set/reset scan flip-flop circuit that normally inhibits active set/reset during scan shift, but allows a set/reset occurring in the last shift cycle to pass through. The circuit may be used in both synchronous and asynchronous scan chain operation. A clock controlled embodiment of the invention also inhibits spurious signals occurring at the beginning of a parallel load cycle.
2. Discussion of the Related Art
FIGS. 1A and 1B show a conventional scan storage element (SSE) and a corresponding scan chain, respectively. When the integrated circuit under test is operating in its normal mode, i.e., the Test Enable (TE) signal is inactive (TE=0), data are loaded into the individual scan storage elements from a data input line D. When in the scan test mode, i.e., the Test Enable signal is active high (TE=1), data are loaded from a scan input line S.sub.i. The scan chain shifts serially when TE=1 and loads data in parallel when TE=0. Loading data into a scan chain from the scan input line S.sub.i when TE=1 is referred to as a scan-in operation. Reading data out of the scan chain from serial output line S.sub.out is referred to as a scan-out operation.
FIG. 2 shows a typical scan flip-flop circuit utilizable in implementing a scan chain. As shown in FIG. 2, because the scan element has both a normal data input D and a scan input S.sub.i, the appropriate input can be selected using a multiplexer controlled by the Test Enable (TE) select signal.
Circuits having set/reset capability, both asynchronous and synchronous, have presented a special challenge to scan operation. The problem is that, when Test Enable is active and shifting is taking place, the set/reset signals must be inhibited to prevent interruption of the serial scan stream.